Layout Design Engineer
Intel
Bengaluru, India
Posted on Jul 13, 2026
🤖 AI Ingested
Full Description
As a Layout Design Engineer, you will be responsible for creating custom layout designs for analog blocks, complex digital and mixed-signal blocks, standard cell libraries, and memory compilers. You will perform detailed physical array planning, layout optimization, and verification using industry-standard EDA tools like Cadence Virtuoso and Calibre to ensure high-performance semiconductor solutions.
Key Stack
Cadence Virtuoso Calibre DRC ICV TCL Python Perl CMOS
Eligibility Details
Batches Eligible 2025, 2026
Estimated Salary Not Disclosed
Job Type Full Time / Hybrid
Date Posted Jul 13, 2026
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